- Software-like Incremental Refinement on FPGA using Partial Reconfiguration
Ph.D. Dissertation, University of Pennsylvania, 2024
Dongjoon Park
- REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), March 2024
(acceptance rate: 22.5% = 20/89)
Dongjoon Park and Andrè DeHon
- ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
ACM Transactions on Reconfigurable Technology and Systems (TRETS), March 2024
Yuanlong Xiao, Dongjoon Park, Zeyu Jaon Niu, Aditya HoTa and Andrè DeHon
- Asymmetry in Butterfly Fat Tree FPGA NoC
IEEE International Conference on Field-Programmable Technology (FPT), December 2023
Dongjoon Park, Zhijing Yao, Yuanlong Xiao and Andrè DeHon
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration
IEEE International Conference on Field-Programmable Technology (FPT), December 2022
(acceptance rate: 25.2% = 31/123)
Artifact Evaluated - Available, Functional, Reusable, Replicated
Dongjoon Park, Yuanlong Xiao, and Andrè DeHon
- HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
IEEE International Conference on Field Programmable Logic and Applications (FPL), August 2022
(Best Paper Nominne: 7.0% = 9/129)
Yuanlong Xiao, Aditya Hota, Dongjoon Park, and Andrè DeHon
- Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
IEEE International Conference on Field-Programmable Technology (FPT), December 2019
(acceptance rate: 25.0% = 26/104)
Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, and Andrè DeHon
- Case for Fast FPGA Compilation using Partial Reconfiguration
IEEE International Conference on Field Programmable Logic and Applications (FPL), August 2018
Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, and Andrè DeHon
